One of the most important building blocks of modern integrated electronic systems is the random access memory array. Important limiting factors in the designs of the systems are the size, speed and power consumption of these memory arrays. Therefore, one of the chief concerns of electronic device designers is to reduce the size of the memory cells comprising these arrays.
A variety of methods have been used to increase the active device density of dynamic random access memory cell arrays. Conventional geometries of the memory cells have formed the pass gate transistors and the storage elements within the surface of the bulk semiconductor substrate. This provides for excellent device characteristics, but inherently uses more semiconductor surface area thereby increasing the memory cell size.
Attempts have been made to construct the constituent parts of the memory cells in a stacked geometry to reduce the cell size. This process requires that at least one or both of the active elements within the memory cell must be constructed outside of the bulk semiconductor substrate material. Using conventional geometries, this resulted in a degradation of the quality of the devices constructed. An additional problem resulting from the use of stacked configurations is that often complex processing steps are required to insure that contact can be made with the inner levels of the memory cell geometry. Contacts with the inner levels of these geometries made away from the memory cell array area occupy valuable substrate surface area.
Therefore, a need has arisen for a memory cell geometry which uses the advantages of the stacked configuration, but which allows for the efficient contacting of inner levels of the cell.